The invention relates to the field of static RAM cells, and, more particularly, to the field of CMOS and MOS static RAM cells.
There is a general trend in the semiconductor industry to make ever more complex semiconductor circuits. The reason is that more complex circuits on single die mean fewer chips are needed to implement functions which reduces the package count. This increases reliability and decreases cost. One of the major trends is toward the use of microprocessors which execute programs stored in memory on data stored in memory. As the complexity of applications becomes ever greater, the software and data to be stored has become ever more voluminous requiring greater quantities of memory. When memory chips could store only 16K bits of data and instructions, complex programs required many memory chips which substantially increased the cost of systems. The trend then has been to make memory cells ever smaller so that more of them can be fit on one die to reduce the cost of memory and increase the reliability of systems using memory.
One of the problems with extremely dense integrated circuit memories is heat dissipation. It is known that certain technologies such as bipolar, ECL and 12 L dissipate large amounts of heat in operation. Other technologies such as NMOS and CMOS use less power but are slightly slower because of greater capacitances associated with MOS devices. Of the MOS technologies, CMOS is well known to dissipate the least amount of power since one device is always "off" thereby limiting the current flowing through the other device which is "on". Thus it is very desirable to make memory cells out of CMOS devices, especially if the capacitance of the memory cell devices and interconnections can be minimized to maximize the speed-power product of the cell.
One way of reducing the capacitance of the cell is to reduce the size of the transistors therein to the minimum size permissible by the photolithographic process. Another way to reduce the overall capacitance of the memory cell is to reduce the overall size of the cell such that the interconnection runs between the devices are of minimum length. This reduces the capacitance between these interconnection conductors and overlying or underlying conductive regions separated from the interconnection conductor by an insulating layer.
One of the impediments to reducing the size of MOS devices is the necessity of making electrical contact with the source, drain and gate electrodes. Electrical contacts are generally made by forming the transistor electrodes and covering them with an insulating layer such as silicon dioxide. Contact windows are then etched through the overlying insulating layer by coating the oxide with a photoresist and exposing portions of the resist layer with radiation directed through a photomask interposed between the radiation source and the photoresist layer. The photoresist is then developed and used as an etch mask during a wet or dry etch process to protect the portions of the oxide that are not to be etched away. The etching process creates a hole through the oxide to the electrodes of the transistors. Then the photoresist is removed and a layer of metal is deposited on the oxide layer. This metal is deposited in the holes and makes contact with the electrodes. Another layer of resist and another mask are then used to form a pattern of conductors in the deposited metal to implement the desired circuit.
The difficulty with this approach in terms of making small transistors is that the contact windows can only be made as small as the smallest line width dimension D which the photolithography process can define. The transistor electrodes must have an area at least as large as that of the contact window to successfully fabricate such a device assuming no alignment errors will occur. In practice however, the transistor electrodes must be made larger than the contact windows so as to provide a clearance around the contact window location to allow for misalignment of the contact window mask with the locations of the electrodes. Thus the electrodes must be made much larger than they would need to be if there were no contact windows needed for connection to the transistor.
Typically static RAM cells involve six transistors two of which must be cross coupled as a flip flop and two of which are connected to the flip flop as load devices. The last two are coupled to the flip flop as addressing devices with their gates coupled to the word line and their channels coupling the bit lines to the output nodes of the flip flop. Obviously there are many interconnections between the electrodes of the various transistors to other electrodes of other transistors. If each interconnection must be made through separate contact windows to the electrodes involved with a metal line running between the contact windows, it can be seen that the size of such a cell is going to be larger than is necessary if the connections could be made without using contact windows.
Accordingly, there has arisen a need for a small MOS device which can be built without contact windows and for a contact windowless memory cell of the static variety using CMOS technology.
Further, in memory design and in other areas of integrated circuit design, it is useful to be able to have both high performance MOS and high performance bipolar devices formed on the same integrated circuit substrate. MOS devices generally are smaller than bipolar devices, but bipolar devices are generally faster than MOS devices. These advantages can be usefully applied in many application areas. Specifically, in memory circuit design, it is useful to use the MOS devices to implement the portions of the circuit where transistors are most populous but where the speed requirements are more relaxed. Where speed is critical such as in the sense amplifiers and decoders, it is useful to be able to use bipolar devices as the operative elements to take advantage of their speed.
Unfortunately, heretofore, the processes that existed to make MOS and bipolar devices on the same die could only make high performance bipolar or high performance MOS transistors but not both on the same die. Accordingly, a need has arisen for a process that can allow the manufacture of both high performance MOS and high performance bipolar transistors on the same integrated circuit die.